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How does a Semiconductor Memory store DATA? [Part 2 Flash Memory, New Memory]

Viewed : 50 times,  2022-01-11 09:04:16

we will learn about PRAM, STT-MRAM, and ferroelectric Memory, which are highlighted recently.

 

(Continued from the previous column) We investigated the storing mechanism of DRAM in Part 1. In Part 2, we will learn about flash memory and briefly summarize the storing mechanism of PRAM, STT-MRAM, and ferroelectric Memory, which are highlighted recently.

 

Storing mechanisms of the flash memory

Flash memory is the same as DRAM as it also stores data using electric charges, but the storage and reading methods are different.

At first, there is no capacitor in a flash memory that can store data in DRAM. How can a flash memory store data only be using a single transistor? The transistor constituting the flash memory cell has three layers in a gate-insulator. The data is stored in a method wherein the charges are stored in the middle layer of a three-layer film. The floating gate (FG) and charge trap nitride (CTN) are the layers storing charges, and it is the CTN method that has recently become mainstream. Flash memory has the advantage of storing more data in a limited area using one transistor.

If it can distinguish whether the electrons are trapped or not, the data can be stored and read. When electrons are trapped, the Vth of the transistor increases. It can read data by detecting these changes. An increase of Vth means that the transistor does not turn on at a certain gate voltage (Vread). In other words, if the electrons are not trapped, the transistor is turned on at the Vread voltage (Data 1), and on the contrary, when the electrons are trapped, the transistor is turned off at the Vread voltage (Data 0). The data are classified using changes in transistor characteristics according to situations where the charges are stored (Figure 1).

 

Figure 1. A flash memory cell. A) When the electrons are not trapped, the transistor turns on at Vread voltage. B) When the electrons are trapped, the transistor turns off at Vread voltage. ([1] D. Richter, Flash Memories – Springer)

Figure 1. A flash memory cell. A) When the electrons are not trapped, the transistor turns on at Vread voltage. B) When the electrons are trapped, the transistor turns off at Vread voltage. ([1] D. Richter, Flash Memories – Springer)

 

In a flash memory cell structure, the three-layer film is composed of a blocking layer / storage layer / tunnel layer, and when a + voltage is applied to the gate for the program, the electrons pass through the tunnel layer and are trapped in the storage layer. To trap electrons as intended, the blocking layer should be formed thicker than the tunnel layer. A method of using a storage layer as polysilicon is the FG method, and a method of using nitride is the CTN method. The CTN method is now mainstream as mentioned above (Figure 2).

 

Figure 2. Program operation for a flash memory cell: When a + voltage is applied in the gate for the program, (b) the electrons are trapped in the storage layer passing by the tunnel layer. The electrons should not be trapped and pass the storage layer (a), or the trapped electrons should not be detrapped (c,d). ([2] R. Micheloni, Inside NAND Flash Memories – Springer)

Figure 2. Program operation for a flash memory cell: When a + voltage is applied in the gate for the program, (b) the electrons are trapped in the storage layer passing by the tunnel layer. The electrons should not be trapped and pass the storage layer (a), or the trapped electrons should not be detrapped (c,d). ([2] R. Micheloni, Inside NAND Flash Memories – Springer)

 

Why are NAND flash memories called NAND? NAND outputs 0 only when all inputs are 1, and 1 in all other cases. Word line (WL), which is not selected when reading NAND flash, makes all 1 by applying voltage Vpass, and current can flow so that the data of a specific cell can be distinguished. Then, the output is determined according to the selected data of the WL, so the data can be distinguished and read. That is, the NAND flash memory cell is organized to output 0 when the data of the addressed cell is 1 and output 1 when the data of the addressed cell is 0 (Figure 3) [2].

 

Figure 3. Schematic of NAND structure cell. All WLs, except addressed cells, are turned on when Vpass is applied. When the addressed cell is turned on this way, the whole is turned on and the BL detects 0, and when the selected cell is turned off, the whole is turned off and the BL detects 1. [2]

Figure 3. Schematic of NAND structure cell. All WLs, except addressed cells, are turned on when Vpass is applied. When the addressed cell is turned on this way, the whole is turned on and the BL detects 0, and when the selected cell is turned off, the whole is turned off and the BL detects 1. [2]

 

The flash cell is currently a 3D structure, not a planar structure. The 3D structure is introduced to overcome cell size limitations. In 2007, Toshiba announced a structure wherein four layers were vertically stacked[3], and in 2015, Samsung announced that 24 layers were stacked[4]. Because the 3D structure is stacked upward, it is possible to increase the data storage capacity per unit area by increasing the layer number and the Vth is easily controlled, making the 3D NAND flash structure currently mainstream. The layer number is steadily increasing, and 176 layers are reported recently (Figure 4) [5].

 

Figure 4. Conceptual diagram of 2D NAND flash structure and 3D NAND flash structure.

Figure 4. Conceptual diagram of 2D NAND flash structure and 3D NAND flash structure. In a 3D structure, the central string forms a channel. A storage element covers around a string, and the entire circumference is wrapped with a word line. Because each layer has a word line and a cell is formed, the memory capacity can be increased by increasing the layer numbers. ([1] D. Richter, Flash Memories – Springer)

 

Meanwhile, a technology that can delicately control the number of trapped electrons has been improved, and a technology that divides Vth into several steps according to the number of electrons has been developed. Now, a cell that can remember (called a Triple Level Cell, or TLC) up to 3 bit (000,001,010,011,100,101,110,111) has already been commercialized.

The trapped electrons remain in their state even when the power is turned off, so it is a nonvolatile memory. The NAND flash memory enables it to become TLC, allowing more data to be stored in a limited area by increasing the layer numbers in a 3D structure. Therefore, the 3D NAND flash memory, which can store large amounts of data at low prices, is largely utilized in various fields.

 

PRAM, STT-MRAM, and Ferroelectric Memory

The DRAM and flash memory store data using charges. However, data can be stored in other ways than using charges. If it can be intentionally changed, maintained, or distinguished, it can serve as a memory device in any way. Therefore, semiconductors memory are not simply DRAM and flash memory. There are several kinds of memory devices such as Phase Change Memory (PRAM), Spin Transfer Torque Magnetic RAM (STT-MRAM), Ferroelectric Memory, etc.

The PRAM stores data using a change of resistance when the material aroused phase change. In other words, 1 and 0 can be distinguished depending on whether the resistance is large or small, inducing a current flow change. There is a commercialized product named Optane Memory in Intel. Like PRAM, STT-MRAM also stores data by distinguishing whether resistance is large or small, and the storing mechanism uses the characteristic of resistance change according to magnetic direction change. The STT-MRAM is mainly adopted in an embedded memory simultaneously fabricated in a logic device.

In addition, although it is still in the research stage, there is a Ferroelectric Memory using polarization of ferroelectrics. In 1950, materials with polarization characteristics of perovskite structures are already applied in memory; however, it was difficult to apply them to cutting-edge semiconductor devices because of their thick thickness. This is because the thickness of BTO, PZT, and SBT, etc., which contain corresponding properties, is around 70 nm, but the cutting-edge semiconductor processes require a thin thickness of several nm or less.

However, as HfO2 containing an orthorhombic structure under certain conditions shows ferroelectricity is reported in 2011, it draws large attention.[6] Because HfO2 is widely used as a high-k material in existing cutting-edge semiconductor processes, it can be enabled to be adopted in cutting-edge semiconductor products. Since then, various studies have been conducted to secure stable ferroelectric properties by doping other materials in HfO2, heat treatment, and control stress, and recently, it has been reported that a real working FeRAM is fabricated (Figure 5).

 

Figure 5. (a) A scanned electron microscopy (SEM) image of 1T 1C FeRAM is shown (in box: MFM capacitor). (b) This is the classification of Data 0 and 1 according to polarization state ([7] J. Okuno, IMW 2021)

Figure 5. (a) A scanned electron microscopy (SEM) image of 1T 1C FeRAM is shown (in box: MFM capacitor). (b) This is the classification of Data 0 and 1 according to polarization state ([7] J. Okuno, IMW 2021)

 

Summary

Semiconductor memory devices are applied to all fields such as personal computers (PC), mobile devices, servers, etc., so the required capacity is increasing. Not only because of a necessity for large capacity but also the need for high performance to read and write a lot of data in a short time is also growing. High-capacity and high-performance memory devices are required to adopt in future cutting-edge technologies such as automatic driving cars and artificial intelligence fields.

It seems that a direction of technological development would have a change in structure and material to overcome the limitations faced in the miniaturization process with high-performance and high-capacity. Technology advances in existing major memory devices such as DRAM and flash memory will continue, and memory devices with new principles using new materials will continue to develop.

 

References

[1] D. Richter, “Flash Memories,” Springer Series in Advanced Microelectronics Vol. 40

[2] R. Micheloni et al., “Inside NAND Flash Memories,” Springer

[3] Y. Fukuzumi et al., “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory,” IEDM Tech. Dig., (2007) pp.449-452

[4] K. T. Park et al., “Three-Dimensional 128Gb MLC Vertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming,” Journal of Solid-State Circuits (2015), pp. 204-213

[5] J. H. Kim et al., “Highly Manufacturable 7th Generation 3D NAND Flash Memory with COP structure and Double Stack Process,” VLSI Symp. Tech. Dig. (2021)

[6] T. S. Boscke et al., “Ferroelectricity in hafnium oxide thin films,” Applied Physics Letters 99, (2011) 102903

[7] J. Okuno et al., “High-Endurance and Low-Voltage operation of 1T1C FeRAM Arrays for Nonvolatile Memory Application,” International Memory Workshop (2021)

 

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In-Ho Nam | Prof. Department Electronic Engineering, Hanyang University

 Author

 In-Ho Nam | Prof. Department of Electronic Engineering, Hanyang University

 ihnam@hanyang.ac.kr


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