The necessity for neuromorphic computing
With the development of artificial intelligence (AI), such applications in a wide range of fields have led to remarkable outcomes, transforming our daily routines in different ways. However, AI technique implementation requires hardware components with a high-power consumption.
In contrast, the human brain consumes only about 20 W of energy despite its ability to carry out higher-level cognitive and learning activities. More attention is being paid to the importance of neuromorphic computing, which aims to embody high-level AI with a lower power consumption by emulating how the human brain works.
Characteristics of neuromorphic computing
The human brain is composed of a network of 1011–12 neurons interconnected by 1014–15 synapses. Neurons get electrically charged in their membranes by input stimuli, and when their membrane potential exceeds a certain threshold voltage, they spike. After that, they transmit electrical impulses to the next neuron via a synapse.
Differing from the existing deep learning–based AI, neuromorphic computing simulates spiking neurons’ temporal characteristics, which are then actively used to implement algorithms. This is called spiking neural networks, distinguished from traditional ones. In neuromorphic computing, operations are carried out only at events when spiking signals are generated.
In other words, because operations are needed to perform specific algorithms, this reduces the number of them needed compared to traditional neural networks and thereby lowers power consumption necessary for specific tasks. In addition, the spike generation immediately responds to input stimuli depending on the environment, so this can also decrease the response latency of a real-time system.
Neuromorphic chips and systems
Neuromorphic computing requires new integrated circuits (ICs) and systems design different from conventional variants. For example, Figure 1 shows the configuration of a large-scale neuromorphic system . Neuromorphic computing seeks to simultaneously emulate the human brain’s structure and the way it works. Spiking neurons and synapses, the basic components necessary for a neuromorphic system, are designed by emulating biological dynamics through IC design.
Figure 1. the configuration of a large-scale neuromorphic system 
There are different mathematical models designed to simulate neuronal dynamics, ranging from the Hodgkin-Huxley model, one of the most biologically plausible models, to the Leaky Integrate-and-Fire model, which only pursues neurons’ most essential characteristics.
Designing neurons by emulating detailed dynamics has the advantage of organizing a system approximating a biological one, but the problem is that it also increases the complexity of integrated circuits used for design. Therefore, to design a large-scale system that integrates neurons on a large-scale, we mostly utilize models simplified through engineering methods by simulating only the key principles of biological neurons.
One example is the Leaky Integrate-and-Fire model, which simulates spike generation when a certain threshold voltage is exceeded by neurons’ accumulated synaptic input. Leaky Integrate-and-Fire neurons are relatively easy to design, thus becoming a popular choice for implementing integrated systems with over a million of them.
Regarding the links between neurons, each of them is interconnected with many other neurons; the link patterns are highly random, so physical connections are impossible in effect. Accordingly, a system is configured in a manner that implements virtual synaptic connections by storing each of them as a data packet in the memory and delivering them when a spike occurs.
Although the data packet encoding rules vary depending on the systems, they include the addresses of target neurons and the strength of synaptic connections. A protocol that allows such virtual connectivity through neurons’ addresses is called the address event representation. Even this representation has a limit to integrating a huge number of neurons (over a million) into one chip.
Hence, some have suggested methods of designing a large-scale neuromorphic system by connecting several chips as one. For example, multiple chips are grouped into a grid, mesh, hierarchical structure, etc. through the event-based protocol. As a result, several neuromorphic chips can be synchronized within a large system.
The future of neuromorphic computing
In this article, neuromorphic chips fabricated through complementary metal-oxide-semiconductor (CMOS)–based IC design techniques were introduced along with the system configuration. Neuromorphic computing is expected to be suitable for implementing AI embedded in systems that can immediately respond and adapt to changes in mobile environments and edge devices that require low power consumption.
More research needs to be conducted on spiking neural network–based algorithms. Spiking neural networks are thought to easily apply to real-time data processing, where a time series is important, because the temporal patterns of spikes generated in response to input stimuli are critical to information processing.
For this reason, they will serve as the brain in such systems as autonomous robots, drones, and more, all of which operate in mobile environments. In addition, it could be possible to design new neural prostheses by utilizing neuromorphic computing characteristics that emulate actual biological systems.
At present, more efforts are being made to study a variety of neuron and synapse fabrication techniques based on new devices. When it comes to those neuronal and synaptic devices, even a single device can act as a neuron and a synapse, so they will be able to increase the degree of integration more dramatically and further reduce power consumption than those made through CMOS-based design. Hopefully, it will be possible to ultimately implement optimal AI consisting of a large neuromorphic system based on new devices, thus emulating the human brain.
 Jongkil Park, Theodore Yu, Siddharth Joshi, Christoph Maier, and Gert Cauwenberghs, “Hierarchical address event routing for reconfigurable large-scale neuromorpjhic systems,” IEEE Transactions on Neural Networks and Learning Systems, vol.28, no. 10, Oct. 2017
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Jongkil Park | Korea Institute of Science and Technology (KIST)